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is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. a 07/20/04 copyright ? 2004 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. july 2004 features ? clock frequency: 200, 166, 143 mhz fully synchronous; all signals referenced to a positive clock edge two banks can be operated simultaneously and independently dual internal bank controlled by a11 (bank select) single 3.3v power supply 2.5v v dd option available lvttl interface programmable burst length ? (1, 2, 4, 8, full page) programmable burst sequence: sequential/interleave 4096 refresh cycles every 64 ms random column address every clock cycle programmable cas latency (2, 3 clocks) burst read/write and burst read/single write operations capability burst termination by burst stop and precharge command byte controlled by ldqm and udqm industrial temperature up to 143 mhz package 400-mil 50-pin tsop ii lead-free package option description issi ?s 16mb synchronous dram is42s16100c1 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. the synchronous drams achieve high-speed data transfer using pipeline architecture. all inputs and outputs signals refer to the rising edge of the clock input. 512k words x 16 bits x 2 banks (16-mbit) synchronous dynamic ram pin configurations 50-pin tsop (type ii) pin descriptions a0-a11 address input a0-a10 row address input a11 bank select address a0-a7 col umn address input dq0 to dq15 data dq clk system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command we write enable ldqm lower bye, input/output mask udqm upper bye, input/output mask vdd power gnd ground vddq power supply for dq pin gndq ground for dq pin nc no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 vdd dq0 dq1 gndq dq2 dq3 vddq dq4 dq5 gndq dq6 dq7 vddq ldqm we cas ras cs a11 a10 a0 a1 a2 a3 vdd gnd dq15 idq14 gndq dq13 dq12 vddq dq11 dq10 gndq dq9 dq8 vddq nc udqm clk cke nc a9 a8 a7 a6 a5 a4 gnd
is42s16100c1 issi ? 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 pin functions pin no. symbol type function (in detail) 20 to 24 a0-a10 input pin a0 to a10 are address inputs. a0-a10 are used as row address inputs during active 27 to 32 command input and a0-a7 as column address inputs during read or write command input. a10 is also used to determine the precharge mode during other commands. if a10 is low during precharge command, the bank selected by a11 is precharged, but if a10 is high, both banks will be precharged. when a10 is high in read or write command cycle, the precharge starts automatically after the burst access. these signals become part of the op code during mode register set command input. 19 a11 input pin a11 is the bank selection signal. when a11 is low, bank 0 is selected and when high, bank 1 is selected. this signal becomes part of the op code during mode register set command input. 16 cas input pin cas , in conjunction with the ras and we , forms the device command. see the ?command truth table? item for details on device commands. 34 cke input pin the cke input determines whether the clk input is enabled within the device. when is cke high, the next rising edge of the clk signal will be valid, and when low, invalid. when cke is low, the device will be in either the power-down mode, the clock suspend mode, or the self refresh mode. the cke is an asynchronous input. 35 clk input pin clk is the master clock input for this device. except for cke, all inputs to this device are acquired in synchronization with the rising edge of this pin. 18 cs input pin the cs input determines whether command input is enabled within the device. command input is enabled when cs is low, and disabled with cs is high. the device remains in the previous state when cs is high. 2, 3, 5, 6, 8, 9, 11 dq0 to dq pin dq0 to dq15 are dq pins. dq through these pins can be controlled in byte units 12, 39, 40, 42, 43, dq15 using the ldqm and udqm pins. 45, 46, 48, 49 14, 36 ldqm, input pin ldqm and udqm control the lower and upper bytes of the dq buffers. in read udqm mode, ldqm and udqm control the output buffer. when ldqm or udqm is low, the corresponding buffer byte is enabled, and when high, disabled. the outputs go to the high impedance state when ldqm/udqm is high. this function corresponds to oe in conventional drams. in write mode, ldqm and udqm control the input buffer. when ldqm or udqm is low, the corresponding buffer byte is enabled, and data can be written to the device. when ldqm or udqm is high, input data is masked and cannot be written to the device. 17 ras input pin ras , in conjunction with cas and we , forms the device command. see the ?command truth table? item for details on device commands. 15 we input pin we , in conjunction with ras and cas , forms the device command. see the ?command truth table? item for details on device commands. 7, 13, 38, 44 vddq power supply pin vddq is the output buffer power supply. 1, 25 vdd power supply pin vdd is the device internal power supply. 4, 10, 41, 47 gndq power supply pin gndq is the output buffer ground. 26, 50 gnd power supply pin gnd is the device internal ground.
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. a 07/21/04 functional block diagram clk cke cs ras cas we a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 command decoder & clock generator mode register refresh controller refresh counter self refresh controller row address latch multiplexer row address buffer row address buffer column address latch burst counter column address buffer row decoder row decoder memory cell array bank 0 column decoder memory cell array bank 1 data in buffer data out buffer sense amp i/o gate sense amp i/o gate 2048 2048 dqm dq 0-1 5 vdd/vddq gnd/gndq 11 11 11 11 8 11 11 8 16 16 16 16 256 256 s16blk.eps
is42s16100c1 issi ? 4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 absolute maximum ratings (1) symbol parameters rating unit v dd max maximum supply voltage ?1.0 to +4.6 v v ddq max maximum supply voltage for output buffer ?1.0 to +4.6 v v in input voltage ?1.0 to +4.6 v v out output voltage ?1.0 to +4.6 v p d max allowable power dissipation 1 w i cs output shorted current 50 ma t opr operating temperature com 0 to +70 c ind. -40 to +85 c t stg storage temperature ?55 to +150 c dc recommended operating conditions (2) ( at t a = 0 to +70c) symbol parameter min. typ. max. unit v dd , v ddq supply voltage 3.0 3.3 3.6 v v ih input high voltage (3) 2.0 ? v dd + 0.3 v v il input low voltage (4) -0.3 ? +0.8 v capacitance characteristics (1,2) (at t a = 0 to +25c, vdd = vddq = 3.3 0.3v, f = 1 mhz) symbol parameter typ. max. unit c in 1 input capacitance: a0-a11 ? 4 pf c in 2 input capacitance: (clk, cke, cs , ras , cas , we , ldqm, udqm) ? 4 pf ci/o data input/output capacitance: dq0-dq15 ? 5 pf notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all voltages are referenced to gnd. 3. v ih (max) = v ddq + 2.0v with a pulse width 3 ns.
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. a 07/21/04 dc electrical characteristics (recommended operation conditions unless otherwise noted.) symbol parameter test condition speed mi n. max. unit i il input leakage current 0v v in vdd, with pins other than ?5 5 a the tested pin at 0v i ol output leakage current output is disabled, 0v v out vdd ?5 5 a v oh output high voltage level i out = ?2 ma 2.4 ? v v ol output low voltage level i out = +2 ma ? 0.4 v i cc1 operating current (1,2) one bank operation, cas latency = 3 com. -5 ? 170 ma burst length=1 com. -6 ? 160 ma t rc t rc (min.) com. -7 ? 140 ma i out = 0ma ind. -7 ? 160 ma i cc2p precharge standby currentcke v il ( max )t ck = t ck ( min ) com. ? ? 3 ma ind. ? ? 4 ma i cc2ps (in power-down mode) t ck = com. ? ? 2 ma ind. ? ? 3 ma i cc3n active standby current cke v ih ( min )t ck = t ck ( min )??40ma i cc3ns (in non power-down mode) t ck = com. ? ? 30 ma ind. ? ? 30 ma i cc4 operating current t ck = t ck ( min ) cas latency = 3 com. -5 ? 170 ma (in burst mode) (1) i out = 0ma com. -6 ? 150 ma com. -7 ? 130 ma ind. -7 ? 150 ma cas latency = 2 com. -5 ? 170 ma com. -6 ? 150 ma com. -7 ? 130 ma ind. -7 ? 150 m i cc5 auto-refresh current t rc = t rc ( min ) cas latency = 3 com. -5 ? 120 ma com. -6 ? 100 ma com. -7 ? 70 ma ind. -7 ? 90 ma cas latency = 2 com. -5 ? 120 ma com. -6 ? 100 ma com. -7 ? 70 ma ind. -7 ? 90 ma i cc6 self-refresh current cke 0.2v ? ? 1 ma notes: 1. these are the values at the minimum cycle time. since the currents are transient, these values decrease as the cycle time increases. also note that a bypass capacitor of at least 0.01 f should be inserted between v dd and gnd for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. icc 1 and icc 4 depend on the output load. the maximum values for icc 1 and icc 4 are obtained with the output open state.
is42s16100c1 issi ? 6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 ac characteristics (1,2,3) -5 -6 -7 symbol parameter min. max. min. max. min. max. units t ck 3 clock cycle time cas latency = 3 5 ? 6 ? 7 ? ns t ck 2 cas latency = 2 8 ? 8 ? 8 ? ns t ac 3 access time from clk (4) cas latency = 3 ? 5 ? 5.5 ? 5.5 ns t ac 2 cas latency = 2 ? 6 ? 6 ? 6 ns t chi clk high level width 2 ? 2.5 ? 2.5 ? ns t cl clk low level width 2 ? 2.5 ? 2.5 ? ns t oh 3 output data hold time cas latency = 3 2 ? 2.0 ? 2.0 ? ns t oh 2 cas latency = 2 2.5 ? 2.5 ? 2.5 ? ns t lz output low impedance time 0 ? 0 ? 0 ? ns t hz 3 output high impedance time (5) cas latency = 3 ? 4 ? 5.5 ? 5.5 ns t hz 2 cas latency = 2 ? 6 ? 6 ? 6 ns t ds input data setup time 2 ? 2 ? 2 ? ns t dh input data hold time 1 ? 1 ? 1 ? ns t as address setup time 1.5 ? 2 ? 2 ? ns t ah address hold time 1 ? 1 ? 1 ? ns t cks cke setup time 1.5 ? 2 ? 2 ? ns t ckh cke hold time 1 ? 1 ? 1 ? ns t cka cke to clk recovery delay time 1clk+3 ? 1clk+3 ? 1clk+3 ? ns t cs command setup time ( cs , ras , cas , we , dqm) 1.5 ? 2 ? 2 ? ns t ch command hold time ( cs , ras , cas , we , dqm) 1 ? 1 ? 1 ? ns t rc command period (ref to ref / act to act) 48 ? 54 ? 63 ? ns t ras command period (act to pre) 32 ? 36 100,000 42 100,000 ns t rp command period (pre to act) 16 ? 18 ? 20 ? ns t rcd active command to read / write command delay time 16 ? 16 ? 16 ? ns t rrd command period (act [0] to act[1]) 11 ? 12 ? 14 ? ns t dpl 3 input data to precharge cas latency = 3 ? 1clk 1clk ? 1clk ? ns command delay time t dpl 2 cas latency = 2 ? 1clk 1clk ? 1clk ? ns t dal 3 input data to active / refresh cas latency = 3 1clk+t rp ? 1clk+t rp ? 1clk+t rp ?ns command delay time (during auto-precharge) t dal 2 cas latency = 2 1clk+t rp ? 1clk+t rp ? 1clk+t rp ?ns t t transition time 1 10 1 10 1 10 ns t ref refresh cycle time (4096) ? 64 ? 64 ? 64 ms notes: 1. when power is first applied, memory operation should be started 100 s after v dd and v ddq reach their stipulated voltages. also note that the power-on sequence must be executed before starting memory operation. 2. measured with t t = 1 ns. 3. the reference level is 1.4 v when measuring input signal timing. rise and fall times are measured between v ih (min.) and v il (max.). 4. access time is measured at 1.4v with the load shown in the figure below. 5. the time t hz (max.) is defined as the time required for the output voltage to transition by 200 mv from v oh (min.) or v ol (max.) when the output is in the high impedance state.
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. a 07/21/04 operating frequency / latency relationships symbol parameter -5 -6 -7 units ? clock cycle time 5 6 7 ns ? operating frequency 200 166 143 mhz t cac cas latency 3 3 3 cycle t rcd active command to read/write command delay time 3 3 3 cycle t rac ras latency (t rcd + t cac ) 6 6 6 cycle t rc command period (ref to ref / act to act) 9 9 9 cycle t ras command period (act to pre) 6 6 6 cycle t rp command period (pre to act) 3 3 3 cycle t rrd command period (act[0] to act [1]) 3 3 3 cycle t ccd column command delay time 1 1 1 cycle (read, reada, writ, writa) t dpl input data to precharge command delay time 1 1 1 cycle t dal input data to active/refresh command delay time 4 4 4 cycle (during auto-precharge) t rbd burst stop command to output in high-z delay time 3 3 3 cycle (read) t wbd burst stop command to input in invalid delay time 0 0 0 cycle (write) t rql precharge command to output in high-z delay time 3 3 3 cycle (read) t wdl precharge command to input in invalid delay time 0 0 0 cycle (write) t pql last output to auto-precharge start time (read) -2 ?2 ?1 cycle t qmd dqm to output delay time (read) 2 2 2 cycle t dmd dqm to input delay time (write) 0 0 0 cycle t mcd mode register set to command delay time 2 2 2 cycle ac test conditions (input/output reference level: 1.4v) i/o 50 ? +1.4v 50 pf output load input t oh t ac 1.4v 1.4v t ch t cs t ck t chi t cl 2.8v 1.4v 0.0v 2.8v 1.4v 0.0v clk input output
is42s16100c1 issi ? 8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 commands clk cke high row row bank 1 bank 0 cs ras cas we a0-a9 a10 a11 clk cke high column bank 1 auto precharge no precharge bank 0 cs ras cas we a0-a9 a10 a11 (1) clk cke high column auto precharge bank 1 bank 0 cs ras cas we a0-a9 a10 a11 clk cke high bank 1 bank 0 and bank 1 bank 0 or bank 1 no precharge bank 0 cs ras cas we a0-a9 a10 a11 (1) notes: 1. a8-a9 = don?t care. don't care active command read command write command precharge command
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. a 07/21/04 commands (cont.) clk cke high cs ras cas we a0-a9 a10 a11 clk cke high cs ras cas we a0-a9 a10 a11 clk cke high cs ras cas we a0-a9 a10 a11 clk cke high cs ras cas we a0-a9 a10 a11 op-code op-code op-code don't care no-operation command device deselect command mode register set command auto-refresh command
is42s16100c1 issi ? 10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 commands (cont.) clk cke cs ras cas we a0-a9 a10 a11 clk cke cs ras cas we a0-a9 a10 a11 bank(s) active high nop nop nop nop clk cke cs ras cas we a0-a9 a10 a11 clk cke cs ras cas we a0-a9 a10 a11 all banks idle nop nop nop nop self-refresh command power down command clock suspend command burst stop command
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. a 07/21/04 mode register set command ( cs , ras , cas , we = low) the is42s16100c1 product incorporates a register that defines the device operating mode. this command functions as a data input pin that loads this register from the pins a0 to a11. when power is first applied, the stipulated power-on sequence should be executed and then the is42s16100c1 should be initialized by executing a mode register set command. note that the mode register set command can be executed only when both banks are in the idle state (i.e. deactivated). another command cannot be executed after a mode register set command until after the passage of the period t mcd , which is the period required for mode register set command execution. active command ( cs , ras = low, cas , we = high) the is42s16100c1 includes two banks of 4096 rows each. this command selects one of the two banks according to the a11 pin and activates the row selected by the pins a0 to a10. this command corresponds to the fall of the ras signal from high to low in conventional drams. precharge command ( cs , ras , we = low, cas = high) this command starts precharging the bank selected by pins a10 and a11. when a10 is high, both banks are precharged at the same time. when a10 is low, the bank selected by a11 is precharged. after executing this command, the next command for the selected bank(s) is executed after passage of the period t rp , which is the period required for bank precharging. this command corresponds to the ras signal from low to high in conventional drams read command ( cs , cas = low, ras , we = high) this command selects the bank specified by the a11 pin and starts a burst read operation at the start address specified by pins a0 to a9. data is output following cas latency. the selected bank must be activated before executing this command. when the a10 pin is high, this command functions as a read with auto-precharge command. after the burst read completes, the bank selected by pin a11 is precharged. when the a10 pin is low, the bank selected by the a11 pin remains in the activated state after the burst read completes. write command ( cs , cas , we = low, ras = high) when burst write mode has been selected with the mode register set command, this command selects the bank specified by the a11 pin and starts a burst write operation at the start address specified by pins a0 to a9. this first data must be input to the dq pins in the cycle in which this command. the selected bank must be activated before executing this command. when a10 pin is high, this command functions as a write with auto-precharge command. after the burst write completes, the bank selected by pin a11 is precharged. when the a10 pin is low, the bank selected by the a11 pin remains in the activated state after the burst write completes. after the input of the last burst write data, the application must wait for the write recovery period (t dpl , t dal ) to elapse according to cas latency. auto-refresh command ( cs , ras , cas = low, we , cke = high) this command executes the auto-refresh operation. the row address and bank to be refreshed are automatically generated during this operation. both banks must be placed in the idle state before executing this command. the stipulated period (t rc ) is required for a single refresh operation, and no other commands can be executed during this period. the device goes to the idle state after the internal refresh operation completes. this command must be executed at least 4096 times every 128 ms. this command corresponds to cbr auto-refresh in conventional drams.
is42s16100c1 issi ? 12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 self-refresh command ( cs , ras , cas , cke = low, we = high) this command executes the self-refresh operation. the row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. the self-refresh operation is started by dropping the cke pin from high to low. the self-refresh operation continues as long as the cke pin remains low and there is no need for external control of any other pins. the self-refresh operation is terminated by raising the cke pin from low to high. the next command cannot be executed until the device internal recovery period (t rc ) has elapsed. after the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an auto-refresh should immediately be performed for all addresses (4096 cycles). both banks must be placed in the idle state before executing this command. burst stop command ( cs , we , = low, ras , cas = high) the command forcibly terminates burst read and write operations. when this command is executed during a burst read operation, data output stops after the cas latency period has elapsed. no operation ( cs , = low, ras , cas , we = high) this command has no effect on the device. device deselect command ( cs = high) this command does not select the device for an object of operation. in other words, it performs no operation with respect to the device. power-down command (cke = low) when both banks are in the idle (inactive) state, or when at least one of the banks is not in the idle (inactive) state, this command can be used to suppress device power dissipation by reducing device internal operations to the absolute minimum. power-down mode is started by dropping the cke pin from high to low. power-down mode continues as long as the cke pin is held low. all pins other than the cke pin are invalid and none of the other commands can be executed in this mode. the power- down operation is terminated by raising the cke pin from low to high. the next command cannot be executed until the recovery period (t cka ) has elapsed. since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (t ref ). thus the maximum time that power-down mode can be held is just under the refresh cycle time. clock suspend (cke = low) this command can be used to stop the device internal clock temporarily during a read or write cycle. clock suspend mode is started by dropping the cke pin from high to low. clock suspend mode continues as long as the cke pin is held low. all input pins other than the cke pin are invalid and none of the other commands can be executed in this mode. also note that the device internal state is maintained. clock suspend mode is terminated by raising the cke pin from low to high, at which point device operation restarts. the next command cannot be executed until the recovery period (t cka ) has elapsed. since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (t ref ). thus the maximum time that clock suspend mode can be held is just under the refresh cycle time.
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. a 07/21/04 command truth table (1,2) cke symbol command n-1 n cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we dqm a11 a10 a9-a0 i/on mrs mode register set (3,4) hxllllx op code x ref auto-refresh (5) h h l l l h x x x x high-z sref self-refresh (5,6) hllllhxx x x high-z pre precharge selected bank h x l l h l x bs l x x pall pr echarge both banks h x l l h l x x h x x act bank activate (7) h x l l h h x bs row row x writ write h x l h l l x bs l column (18) x writa w rite with auto-precharge (8) h x l h l l x bs h column (18) x read read (8) h x l h l h x bs l column (18) x reada read with auto-precharge (8) h x l h l h x bs h column (18) x bst burst stop (9) hxlhhlxxxx x nop no operation h x l hhhxx x x x desl device deselect h x h xxxxx x x x sby clock suspend / standby mode l xxxxxxx x x x enb data write / output enable h xxxxxlx x x active mask data mask / output disable h xxxxxhx x x high-z dqm truth table (1,2) cke dqm symbol command n-1 n upper lower enb data write / output enable h x l l mask data mask / output disable h x h h enbu u pper byte data write / output enable h x l x enbl lower byte d ata write / output enable h x x l masku upper byte data mask / output disable h x h x maskl lower byte data mask / output disable h x x h cke truth table (1,2) cke symbol command current state n-1 n cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we a11 a10 a9-a0 spnd start cl ock suspend mode active h l xxxxxxx ? clock suspend other states l l xxxxxxx ? terminate clock suspend mode clock suspend l h xxxxxxx ref auto-refresh idle h h l l l h x x x self start self-refresh mode idle h llllhxxx selfx terminate self-refresh mode self-refresh l h l hhhxxx lhhxxxxxx pdwn start power-down mode idle h l l hhhxxx hlhxxxxxx ? terminate power-down mode power-down l h xxxxxxx
is42s16100c1 issi ? 14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 operation command table (1,2) current state command operation cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we a11 a10 a9-a0 idl e desl no o peration or power-down (12) hxxxxxx nop no operation or power-down (12) lhhhxxx bst no operation or power-down l h h l x x x read / reada illegal l h l h v v v (18) writ/writa illegal l h l l v v v (18) act row active l l h h v v v (18) pre/pall no operation l l h l v v x ref/self auto-refresh or self-refresh (13) lllhxxx mrs mode register set llll op code row active desl no operation h xxxxxx nop no operation l h h h x x x bst no operation l h h l x x x read/reada read start (17) lhlhvvv (18) writ/writa write start (17) lhllvvv (18) act illegal (10) llhhvvv (18) pre/pall precharge (15) l lhlvvx ref/self illegal l l l h x x x mrs illegal llll op code read desl burst read continues, row active when done h xxxxxx nop burst read continues, row active when done l h h h x x x bst burst interrupted, row active after interrupt l h h l x x x read/reada burst interrupted, read restart after interrupt (16) lhlhvvv (18) writ/writa burst interrupted write start after interrupt (11,16) lhllvvv (18) act illegal (10) llhhvvv (18) pre/pall burst read interrupted, precharge after interrupt l l h l v v x ref/self illegal l l l h x x x mrs illegal llll op code write desl burst write continues, write recovery when done h xxxxxx nop burst write continues, write recovery when done l h h h x x x bst burst write interrupted, row active after interrupt l h h l x x x read/reada burst write interrupted, read start after interrupt (11,16) lhlhvvv (18) writ/writa burst write interrupted, write restart after interrupt (16) lhllvvv (18) act illegal (10) llhhvvv (18) pre/pall burst write interrupted, precharge after interrupt l l h l v v x ref/self illegal l l l h x x x mrs illegal llll op code read with desl burst read continues, precharge when done h xxxxxx auto- nop burst read continues, precharge when done l h h h x x x precharge bst illegal l h h l x x x read/reada illegal l h l h v v v (18) writ/writa illegal l h l l v v v (18) act illegal (10) llhhvvv (18) pre/pall illegal (10) l lhlvvx ref/self illegal l l l h x x x mrs illegal llll op code
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 rev. a 07/21/04 operation command table (1,2) current state command operation cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we a11 a10 a9-a0 write with desl burst write continues, write recovery and precharge h xxxxxx auto-precharge when done nop burst write continues, write recovery and precharge l hhhxxx bst illegal l h h l x x x read/reada illegal l h l h v v v (18) writ/writa illegal l h l l v v v (18) act illegal (10) llhhvvv (18) pre/pall illegal (10) l lhlvvx ref/self illegal l l l h x x x mrs illegal llll opcode row precharge desl no operation, idle state after t rp has elapsed h xxxxxx nop no operation, idle state after t rp has elapsed l h h h x x x bst no operation, idle state after t rp has elapsed lhhlxxx read/reada illegal (10) lhlhvvv (18) writ/writa illegal (10) lhllvvv (18) act illegal (10) llhhvvv (18) pre/pall no operation, idle state after t rp has elapsed (10) l lhlvvx ref/self illegal l l l h x x x mrs illegal llll op code immediately desl no operation, row active after t rcd has elapsed h xxxxxx following nop no operation, row active after t rcd has elapsed l h h h x x x row active bst no operation, row active after t rcd has elapsed l h h l x x x read/reada illegal (10) lhlhvvv (18) writ/writa illegal (10) lhllvvv (18) act illegal (10,14) l lhhvvv (18) pre/pall illegal (10) l lhlvvx ref/self illegal l l l h x x x mrs illegal llll op code write desl no operation, row active after t dpl has elapsedh xxxxxx recovery nop no operation, row active after t dpl has elapsed l h h h x x x bst no operation, row active after t dpl has elapsed lhhlxxx read/reada read start l h l h v v v (18) writ/writa write restart l h l l v v v (18) act illegal (10) l lhhvvv (18) pre/pall illegal (10) l lhlvvx ref/self illegal l l l h x x x mrs illegal llll op code
is42s16100c1 issi ? 16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 operation command table (1,2) current state command operation cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we a11 a10 a9-a0 write recovery desl no operation, idle state after t dal has elapsed h xxxxxx with auto- nop no operation, idle state after t dal has elapsed l h h h x x x precharge bst no operation, idle state after t dal has elapsed l h h l x x x read/reada illegal (10) lhlhvvv (18) writ/writa illegal (10) lhllvvv (18) act illegal (10) llhhvvv (18) pre/pall illegal (10) l lhlvvx ref/self illegal l l l h x x x mrs illegal llll op code refresh desl no operation, idle state after t rp has elapsed h xxxxxx nop no operation, idle state after t rp has elapsed l h h h x x x bst no operation, idle state after t rp has elapsed l h h l x x x read/reada illegal l h l h v v v (18) writ/writa illegal l h l l v v v (18) act illegal l l h h v v v (18) pre/pall illegal l l h l v v x ref/self illegal l l l h x x x mrs illegal llll op code mode register desl no operation, idle state after t mcd has elapsed h xxxxxx set nop no operation, idle state after t mcd has elapsed l h h h x x x bst no operation, idle state after t mcd has elapsed l h h l x x x read/reada illegal l h l h v v v (18) writ/writa illegal l h l l v v v (18) act illegal l l h h v v v (18) pre/pall illegal l l h l v v x ref/self illegal l l l h x x x mrs illegal llll op code notes: 1. h: high level input, l: low level input, x: high or low level input, v: valid data input 2. all input signals are latched on the rising edge of the clk signal. 3. both banks must be placed in the inactive (idle) state in advance. 4. the state of the a0 to a11 pins is loaded into the mode register as an op code. 5. the row address is generated automatically internally at this time. the dq pin and the address pin data is ignored. 6. during a self-refresh operation, all pin data (states) other than cke is ignored. 7. the selected bank must be placed in the inactive (idle) state in advance. 8. the selected bank must be placed in the active state in advance. 9. this command is valid only when the burst length set to full page. 10. this is possible depending on the state of the bank selected by the a11 pin. 11. time to switch internal busses is required. 12. the is42s16100c1 can be switched to power-down mode by dropping the cke pin low when both banks in the idle state. input pins other than cke are ignored at this time. 13. the is42s16100c1 can be switched to self-refresh mode by dropping the cke pin low when both banks in the idle state. input pins other than cke are ignored at this time. 14. possible if t rrd is satisfied. 15. illegal if t ras is not satisfied. 16. the conditions for burst interruption must be observed. also note that the is42s16100c1 will enter the precharged state immediately after the burst operation completes if auto-precharge is selected. 17. command input becomes possible after the period t rcd has elapsed. also note that the is42s16100c1 will enter the precharged state immediately after the burst operation completes if auto-precharge is selected. 18. a8,a9 = don?t care.
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 rev. a 07/21/04 cke related command truth table (1) cke current state operation n-1 n cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we a11 a10 a9-a0 self-refresh undefined h x xxxxxxx self-refresh recovery (2) lhhxxxxxx self-refresh recovery (2) lhlhhxxxx illegal (2) lhlhlxxxx illegal (2) lhl lxxxxx self-refresh l l xxxxxxx self-refresh recovery idle state after t rc has elapsed h h h xxxxxx idle state after t rc has elapsed h h l h h xxxx illegal h h l h l xxxx illegal h h l l xxxxx power-down on the next cycle h l h xxxxxx power-down on the next cycle h l l h h xxxx illegal h l l h l xxxx illegal h l l l xxxxx clock suspend termination on the next cycle (2) lhxxxxxxx clock suspend l l xxxxxxx power-down undefined h x xxxxxxx power-down mode termination, idle after l h xxxxxxx that termination (2) power-down mode l l xxxxxxx both banks idle no operation h h h xxxxxx see the operation command table h h l h xxxxx bank active or precharge h h l l h xxxx auto-refresh h h l l l h x x x mode register set h h llll op code see the operation command table h l h xxxxxx see the operation command table h l l h xxxxx see the operation command table h l l l h xxxx self-refresh (3) hllllhxxx see the operation command table h lllll op code power-down mode (3) lxxxxxxxx other states see the operation command table h h xxxxxxx clock suspend on the next cycle (4) hlxxxxxxx clock suspend termination on the next cycle l h xxxxxxx clock suspend termination on the next cyclel l xxxxxxx notes: 1. h: high level input, l: low level input, x: high or low level input 2. the clk pin and the other input are reactivated asynchronously by the transition of the cke level from low to high. the minimum setup time (t cka ) required before all commands other than mode termination must be satisfied. 3. both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode. 4. the input must be command defined in the operation command table.
is42s16100c1 issi ? 18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 two banks operation command truth table (1,2) previous state next state operation cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we a11 a10 a9-a0 bank 0bank 1 bank 0bank 1 desl h xxxxxx any any any any nop l h h h x x x any any any any bst l h h l x x x r/w/a i/a a i/a i i/a i i/a i/a r/w/a i/a a i/a i i/a i read/reada l h l h h h ca (3) i/a r/w/a i/a rp hhca (3) r/w a a rp hlca (3) i/a r/w/a i/a r hlca (3) r/w a a r lhca (3) r/w/a i/a rp i/a lhca (3) a r/w rp a llca (3) r/w/a i/a r i/a llca (3) a r/w r a writ/writa l h l l h h ca (3) i/a r/w/a i/a wp hhca (3) r/w a a wp hlca (3) i/a r/w/a i/a w hlca (3) r/w a a w lhca (3) r/w/a i/a wp i/a lhca (3) a r/w wp a llca (3) r/w/a i/a w i/a llca (3) a r/w w a act l l h h h ra ra any i any a l ra ra i any a any pre/pall l l h l x h x r/w/a/i i/a i i x h x i/a r/w/a/i i i h l x i/a r/w/a/i i/a i h l x r/w/a/i i/a r/w/a/i i l l x r/w/a/i i/a i i/a l l x i/a r/w/a/i i r/w/a/i ref lllhxxx ii ii mrs llll opcode i i i i notes: 1. h: high level input, l: low level input, x: high or low level input, ra: row address, ca: column address 2. the device state symbols are interpreted as follows: i idle (inactive state) a row active state r read w write rp read with auto-precharge wp write with auto-precharge any any state 3. ca: a8,a9 = don?t care.
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 rev. a 07/21/04 simplified state transition diagram (one bank operation) self refresh auto refresh idle power down active power down idle mode register set read bank active write clock suspend read with auto precharge pre- charge power on write with auto precharge clock suspend transition due to command input. automatic transition following the completion of command execution. mrs sref entry sref exit ref cke_ cke act cke_ cke bst bst read cke_ cke reada cke_ cke read reada read writa writ writ cke_ cke writa cke_ cke writ writa pre pre reada pre pre power applied
is42s16100c1 issi ? 20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 device initialization at power-on (power-on sequence) as is the case with conventional drams, the is42s16100c1 product must be initialized by executing a stipulated power-on sequence after power is applied. after power is applied and vdd and vddq reach their stipulated voltages, set and hold the cke and dqm pins high for 100 s. then, execute the precharge command to precharge both bank. next, execute the auto-refresh command twice or more and define the device operation mode by executing a mode register set command. the mode register set command can be also set before auto-refresh command. mode register settings the mode register set command sets the mode register. when this command is executed, pins a0 to a9, a10, and a11 function as data input pins for setting the register, and this data becomes the device internal op code. this op code has four fields as listed in the table below. note that the mode register set command can be executed only when both banks are in the idle (inactive) state. wait at least two cycles after executing a mode register set command before executing the next command. cas cas cas cas cas latency during a read operation, the between the execution of the read command and data output is stipulated as the cas latency. this period can be set using the mode register set command. the optimal cas latency is determined by the clock frequency and device speed grade (-10/12). see the ?operating frequency / latency relationships? item for details on the relationship between the clock frequency and the cas latency. see the table on the next page for details on setting the mode register. input pin field a11, a10, a9, a8 mode options a6, a5, a4 cas latency a3 burst type a2, a1, a0 burst length burst length when writing or reading, data can be input or output data continuously. in these operations, an address is input only once and that address is taken as the starting address internally by the device. the device then automatically generates the following address. the burst length field in the mode register stipulates the number of data items input or output in sequence. in the is42s16100c1 product, a burst length of 1, 2, 4, 8, or full page can be specified. see the table on the next page for details on setting the mode register. burst type the burst data order during a read or write operation is stipulated by the burst type, which can be set by the mode register set command. the is42s16100c1 product supports sequential mode and interleaved mode burst type settings. see the table on the next page for details on setting the mode register. see the ?burst length and column address sequence? item for details on dq data orders in these modes. write mode burst write or single write mode is selected by the op code (a11, a10, a9) of the mode register. a burst write operation is enabled by setting the op code (a11, a10, a9) to (0,0,0). a burst write starts on the same cycle as a write command set. the write start address is specified by the column address and bank select address at the write command set cycle. a single write operation is enabled by setting op code (a11, a10, a9) to (1,0,0). in a single write operation, data is only written to the column address and bank select address specified by the write command set cycle without regard to the bust length setting.
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 rev. a 07/21/04 mode register m2 m1 m0 sequential interleaved burst length 0 0 0 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved 111098 76 54 32 10 write mode lt mode bt bl m3 type burst type 0 sequential 1 interleaved m6 m5 m4 cas cas cas cas cas latency latency mode 0 0 0 reserved 0 0 1 reserved 010 2 011 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved m11 m10 m9 m8 m7 write mode x x 0 0 0 mode register set x x 1 0 0 burst read & single write 00000 reserved test set address bus mode register (mx)
is42s16100c1 issi ? 22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 burst length and column address sequence column address address sequence burst length a2 a1 a0 sequential interleaved 2 x x 0 0-1 0-1 x x 1 1-0 1-0 4 x 0 0 0-1-2-3 0-1-2-3 x 0 1 1-2-3-0 1-0-3-2 x 1 0 2-3-0-1 2-3-0-1 x 1 1 3-0-1-2 3-2-1-0 8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page n n n cn, cn+1, cn+2 none (256) cn+3, cn+4..... ...cn-1(cn+255), cn(cn+256)..... notes: 1. the burst length in full page mode is 256.
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 rev. a 07/21/04 bank select and precharge address allocation row x0 ? row address x1 ? row address x2 ? row address x3 ? row address x4 ? row address x5 ? row address x6 ? row address x7 ? row address x8 ? row address x9 ? row address x10 0 precharge of the select ed bank (precharge command) row address 1 precharge of both banks (precharge command) (active command) x11 0 bank 0 selected (precharge and active command) 1 bank 1 selected (precharge and active command) column y0 ? column address y1 ? column address y2 ? column address y3 ? column address y4 ? column address y5 ? column address y6 ? column address y7 ? column address y8 ? don?t care y9 ? don?t care y10 0 auto-precharge - disabled 1 auto-precharge - enables y11 0 bank 0 selected (read and write commands) 1 bank 1 selected (read and write commands)
is42s16100c1 issi ? 24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 burst read the read cycle is started by executing the read command. the address provided during read command execution is used as the starting address. first, the data corresponding to this address is output in synchronization with the clock signal after the cas latency period. next, data corresponding to an address generated automatically by the device is output in synchronization with the clock signal. the output buffers go to the low impedance state cas latency minus one cycle after the read command, and go to the high impedance state automatically after the last data is output. however, the case where the burst length is a full page is an exception. in this case the output buffers must be set to the high impedance state by executing a burst stop command. note that upper byte and lower byte output data can be masked independently under control of the signals applied to the u/ldqm pins. the delay period (t qmd ) is fixed at two, regardless of the cas latency setting, when this function is used. the selected bank must be set to the active state before executing this command. cas latency = 3, burst length = 4 burst write the write cycle is started by executing the command. the address provided during write command execution is used as the starting address, and at the same time, data for this address is input in synchronization with the clock signal. next, data is input in other in synchronization with the clock signal. during this operation, data is written to address generated automatically by the device. this cycle terminates automatically after a number of clock cycles determined by the stipulated burst length. however, the case where the burst length is a full page is an exception. in this case the write cycle must be terminated by executing a burst stop command. the latency for dq pin data input is zero, regardless of the cas latency setting. however, a wait period (write recovery: t dpl ) after the last data input is required for the device to complete the write operation. note that the upper byte and lower byte input data can be masked independently under control of the signals applied to the u/ldqm pins. the delay period (t dmd ) is fixed at zero, regardless of the cas latency setting, when this function is used. the selected bank must be set to the active state before executing this command. cas latency = 2,3, burst length = 4 read a0 command udqm ldqm dq8-dq15 dq0-dq 7 clk d out a0 t qmd=2 hi-z hi-z hi-z read (ca=a, bank 0) data mask (lower byte) data mask (upper byte) d out a2 d out a3 d out a1 d out a0 burst length write command dq clk d in 0d in 1d in 2d in 3
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 rev. a 07/21/04 read with auto-precharge the read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. after the precharge com- pletes, the bank goes to the idle state. thus this command performs a read command and a precharge command in a single operation. during this operation, the delay period (t pql ) between the last burst data output and the start of the precharge operation differs depending on the cas latency setting. when the cas latency setting is two, the precharge operation starts on one clock cycle before the last burst data is output (t pql = ?1). when the cas latency setting is three, the precharge operation starts on two clock cycles before the last burst data is output (t pql = ?2). therefore, the selected bank can be made active after a delay of t rp from the start position of this precharge operation. the selected bank must be set to the active state before executing this command. the auto-precharge function is invalid if the burst length is set to full page. cas cas cas cas cas latency 3 2 t pql ?2 ?1 command dq clk t rp t pql reada 0 act 0 precharge start read with auto-precharge (bank 0) d out 0d out 1d out 2d out 3 command dq clk reada 0 act 0 t rp precharge start read with auto-precharge (bank 0) t pql d out 0d out 1d out 2d out 3 cas latency = 2, burstlength = 4 cas latency = 3, burstlength = 4
is42s16100c1 issi ? 26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write with auto-precharge the write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. after the precharge completes the bank goes to the idle state. thus this command performs a write command and a precharge command in a single operation. during this operation, the delay period (t dal ) between the last burst data input and the completion of the precharge operation differs depending on the cas latency setting. the delay (t dal ) is t rp plus one clk period. that is, the precharge operation starts one clock period after the last burst data input. therefore, the selected bank can be made active after a delay of t dal . the selected bank must be set to the active state before executing this command. the auto-precharge function is invalid if the burst length is set to full page. cas cas cas cas cas latency 3 2 t dal 1clk 1clk +t rp +t rp t rp t dal precharge start dq write a0 command clk act 0 write with auto-precharge (bank 0) t rp t dal precharge start write a0 command dq clk d in 0d in 1d in 2d in 3 act 0 write with auto-precharge (bank 0) d in 0d in 1d in 2d in 3 cas latency = 2, burstlength = 4 cas latency = 3, burstlength = 4
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 rev. a 07/21/04 interval between read command a new command can be executed while a read cycle is in progress, i.e., before that cycle completes. when the second read command is executed, after the cas latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command. the interval between two read command (t ccd ) must be at least one clock cycle. the selected bank must be set to the active state before executing this command. interval between write command a new command can be executed while a write cycle is in progress, i.e., before that cycle completes. at the point the second write command is executed, data corresponding to the new write command can be input in place of the data for the previous write command. the interval between two write commands (t ccd ) must be at least one clock cycle. the selected bank must be set to the active state before executing this command. read a0 read b0 command dq clk d out a0 d out b0 d out b1 d out b2 read (ca=a, bank 0) read (ca=b, bank 0) t ccd d out b3 cas latency = 2, burstlength = 4 write a0 write b0 command dq clk d in a0 d in b0 d in b1 d in b2 d in b3 write (ca=a, bank 0) write (ca=b, bank 0) t ccd cas latency = 3, burstlength = 4
is42s16100c1 issi ? 28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 interval between write and read commands a new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. data corresponding to the new read command is output after the cas latency has elapsed from the point the new read command was executed. the i/on pins must be placed in the high impedance state at least one cycle before data is output during this operation. the interval (t ccd ) between command must be at least one clock cycle. the selected bank must be set to the active state before executing this command. dq write a0 read b0 command clk d in a0 d out b0 d out b2 d out b1 d out b3 t ccd hi-z write ( ca=a, bank 0 ) read ( ca=b, bank 0 ) dq write a0 read b0 command clk d in a0 d out b0 d out b2 d out b1 d out b3 t ccd hi-z write (ca=a, bank 0) read (ca=b, bank 0) cas latency = 2, burstlength = 4 cas latency = 3, burstlength = 4
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 rev. a 07/21/04 interval between read and write commands a read command can be interrupted and a new write command executed while the read cycle is in progress, i.e., before that cycle completes. data corresponding to the new write command can be input at the point new write command is executed. to prevent collision between input and output data at the dqn pins during this operation, the output data must be masked using the u/ldqm pins. the interval (t ccd ) between these commands must be at least one clock cycle. the selected bank must be set to the active state before executing this command. write b0 read a0 command u/ldqm dq clk d in b0 d in b2 d in b1 d in b3 t ccd hi-z read (ca=a, bank 0) write (ca=b, bank 0) cas latency = 2, 3, burstlength = 4
is42s16100c1 issi ? 30 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 precharge the precharge command sets the bank selected by pin a11 to the precharged state. this command can be executed at a time t ras following the execution of an active command to the same bank. the selected bank goes to the idle state at a time t rp following the execution of the precharge command, and an active command can be executed again for that bank. if pin a10 is low when this command is executed, the bank selected by pin a11 will be precharged, and if pin a10 is high, both banks will be precharged at the same time. this input to pin a11 is ignored in the latter case. read cycle interruption using the precharge command a read cycle can be interrupted by the execution of the precharge command before that cycle completes. the delay time (t rql ) from the execution of the precharge command to the completion of the burst output is the clock cycle of cas latency. cas cas cas cas cas latency 3 2 t rql 32 t rql t rql pre 0 read a0 command dq clk d out a0 d out a1 d out a2 hi-z read (ca=a, bank 0) precharge (bank 0) pre 0 read a0 command dq clk d out a0 d out a1 d out a2 hi-z read ( ca=a, bank 0 ) precharge ( bank 0 ) cas latency = 2, burstlength = 4 cas latency = 3, burstlength = 4
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 31 rev. a 07/21/04 write cycle interruption using the precharge command a write cycle can be interrupted by the execution of the precharge command before that cycle completes. the delay time (t wdl ) from the precharge command to the point where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the cas . to inhibit invalid write, the dqm signal must be asserted high with the precharge command. this precharge command and burst write command must be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual bank operation. inversely, to write all the burst data to the device, the precharge command must be executed after the write data recovery period (t dpl ) has elapsed. therefore, the precharge command must be executed on one clock cycle that follows the input of the last burst data item. cas cas cas cas cas latency 3 2 t wdl 00 t dpl 11 pre 0 write a0 command dqm dq clk d in a0 d in a1 d in a2 d in a3 t wdl =0 write (ca=a, bank 0) precharge (bank 0) masked by dqm pre 0 write a0 command dq clk d in a0 d in a1 d in a2 d in a3 t dpl write (ca=a, bank 0) precharge (bank 0) cas latency = 2, burstlength = 4 cas latency = 3, burstlength = 4
is42s16100c1 issi ? 32 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle (full page) interruption using the burst stop command the is42s16100c1 can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. the is42s16100c1 repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. a burst stop command must be executed to terminate this cycle. a precharge command must be executed within the act to pre command period (t ras max.) following the burst stop command. after the period (t rbd ) required for burst data output to stop following the execution of the burst stop command has elapsed, the outputs go to the high impedance state. this period (t rbd ) is two clock cycle when the cas latency is two and three clock cycle when the cas latency is three. cas cas cas cas cas latency 3 2 t rbd 32 bst read a0 command dq clk t rbd read (ca=a, bank 0) burst stop hi-z d out a0 d out a0 d out a1 d out a2 command dq clk t rbd read a0 read (ca=a, bank 0) burst stop bst hi-z d out a0 d out a0 d out a1 d out a2 d out a3 d out a3 c a s latency = 3, burstlength = 4 cas latency = 2, burstlength = 4
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 33 rev. a 07/21/04 write cycle (full page) interruption using the burst stop command the is42s16100c1 can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full page. the is42s16100c1 repeats the operation starting at the 256th cycle with data input returning to location (a) and continuing with a+1, a+2, a+3, etc. a burst stop command must be executed to terminate this cycle. a precharge command must be executed within the act to pre command period (t ras max.) following the burst stop command. after the period (t wbd ) required for burst data input to stop following the execution of the burst stop command has elapsed, the write cycle terminates. this period (t wbd ) is zero clock cycles, regardless of the cas latency. burst data interruption using the u/ldqm pins (read cycle) burst data output can be temporarily interrupted (masked) during a read cycle using the u/ldqm pins. regardless of the cas latency, two clock cycles (t qmd ) after one of the u/ ldqm pins goes high, the corresponding outputs go to the high impedance state. subsequently, the outputs are maintained in the high impedance state as long as that u/ ldqm pin remains high. when the u/ldqm pin goes low, output is resumed at a time t qmd later. this output control operates independently on a byte basis with the udqm pin controlling upper byte output (pins dq8-dq15) and the ldqm pin controlling lower byte output (pins dq0 to dq7). since the u/ldqm pins control the device output buffers only, the read cycle continues internally and, in particular, incrementing of the internal burst counter continues. cas latency = 2, burstlength = 4 read a0 command udqm ldqm dq8-dq15 dq0-dq 7 clk d out a0 t qmd=2 hi-z hi-z hi-z read (ca=a, bank 0) data mask (lower byte) data mask (upper byte) d out a2 d out a3 d out a1 d out a0 write a0 command dq clk d in a0 d in a1 d in ad in a1 d in a2 t wbd=0 t rp read (ca=a, bank 0) burst stop bst pre 0 invalid data precharge (bank 0) don't care
is42s16100c1 issi ? 34 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 burst data interruption u/ldqm pins (write cycle) burst data input can be temporarily interrupted (muted ) during a write cycle using the u/ldqm pins. regardless of the cas latency, as soon as one of the u/ldqm pins goes high, the corresponding externally applied input data will no longer be written to the device internal circuits. subsequently, the corresponding input continues to be muted as long as that u/ldqm pin remains high. the is42s16100c1 will revert to accepting input as soon as that pin is dropped to low and data will be written to the device. this input control operates independently on a byte basis with the udqm pin controlling upper byte input (pin dq8 to dq15) and the ldqm pin controlling the lower byte input (pins dq0 to dq7). since the u/ldqm pins control the device input buffers only, the cycle continues internally and, in particular, incrementing of the internal burst counter continues. burst read and single write the burst read and single write mode is set up using the mode register set command. during this operation, the burst read cycle operates normally, but the write cycle only writes a single data item for each write cycle. the cas latency and dqm latency are the same as in normal mode. write a0 command udqm ldqm dq8-dq15 dq0-dq7 clk d in a1 write (ca=a, bank 0) data mask (lower byte) data mask (upper byte) t dmd=0 d in a2 d in a3 d in a0 d in a3 don't care cas latency = 2, 3 cas latency = 2, burstlength = 4 write a0 command dq clk d in a0 write (ca=a, bank 0)
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 35 rev. a 07/21/04 bank active command interval when the selected bank is precharged, the period trp has elapsed and the bank has entered the idle state, the bank can be activated by executing the active command. if the other bank is in the idle state at that time, the active command can be executed for that bank after the period t rrd has elapsed. at that point both banks will be in the active state. when a bank active command has been executed, a precharge command must be executed for that bank within the act to pre command period (t ras max). also note that a precharge command cannot be executed for an active bank before t ras (min) has elapsed. after a bank active command has been executed and the trcd period has elapsed, read write (including auto-precharge) commands can be executed for that bank. act 0 act 1 command clk bank active (bank 0) bank active (bank 1) t rrd act 0 read 0 command clk bank active (bank 0) bank active (bank 0) t rcd cas latency = 3 clock suspend when the cke pin is dropped from high to low during a read or write cycle, the is42s16100c1 enters clock suspend mode on the next clk rising edge. this command reduces the device power dissipation by stopping the device internal clock. clock suspend mode continues as long as the cke pin remains low. in this state, all inputs other than cke pin are invalid and no other commands can be executed. also, the device internal states are maintained. when the cke pin goes from low to high clock suspend mode is terminated on the next clk rising edge and device operation resumes. the next command cannot be executed until the recovery period (t cka ) has elapsed. since this command differs from the self-refresh command described previously in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tref). thus the maximum time that clock suspend mode can be held is just under the refresh cycle time. read 0 command cke dq clk d out 0d out 1d out 2d out 3 read (bank 0) clock suspend cas latency = 2, burstlength = 4
is42s16100c1 issi ? 36 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 operation timing example power-on sequence, mode register set cycle clk cke high high cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t10 t17 t18 t19 t20 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 0 & 1 t ah t as t ah t as t ah t as code code code row row bank 1 bank 0 wait time t=100 s t rp t rc t rc t mcd t ras t rc < act > < mrs > < ref > < pall >< ref > cas latency = 2, 3 don't care undefined
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 37 rev. a 07/21/04 power-down mode cycle clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 tn tn+1 tn+2 tn+3 t ck t cks t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as row row bank 1 bank 0 t cks t ckh t cka t cka t ah t as t rp power down mode exit power down mode t ras t rc < act > < sby > < pre > < pall > bank 0 & 1 bank 0 or 1 bank 1 bank 0 cas latency = 2, 3 don't care undefined
is42s16100c1 issi ? 38 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 cas latency = 2, 3 auto-refresh cycle clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 tl tm tn tn+1 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 0 & 1 row row bank 1 bank 0 t rp t rc t rc t rc t ras t rc < act > < ref >< ref > < pall >< ref > t cks don't care undefined
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 39 rev. a 07/21/04 cas latency = 2, 3 self-refresh cycle don't care undefined clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 tm tm+2 tm+1 tn t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 0 & 1 t cks t cks t cka t cka t rp self refresh mode exit self refresh t rc t rc < ref > < pall >< self > t cks note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 40 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 c a s latency = 2, burstlength = 4 don't care undefined clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 and 1 bank 0 or 1 no pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 bank 1 bank 0 row row row column m row t qmd t lz t ras t rc < act >< read > < act > < pre > < pall > t rcd t cac t rql t rp t rcd t ac t ac t oh t ac t ac t oh t ch t oh d out md out m+1 d out m+2 t oh t hz d out m+3 t rc t ras (1) read cycle note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 41 rev. a 07/21/04 c a s latency = 2, burstlength = 4 don't care undefined clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 auto pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 row row row column m row t qmd t lz t ras t rc < act >< reada > < act > t rcd t cac t pql t rp t rcd t ac t ac t oh t ac t ac t oh t ch t oh d out md out m+1 d out m+2 t oh t hz d out m+3 t rc t ras (1) read cycle / auto-precharge note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 42 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle / full page clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t260 t261 t262 t263 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 0 or 1 bank 0 row column row t qmd t lz t ras t rc (bank 0) < act 0 >< read0 > < bst >< pre 0 > t rcd t cac (bank 0) t rbd t ac t ac t oh t ac t ac t ac t oh t ch t oh d out 0m d out 0m+1 d out 0m-1 t oh t hz t oh d out 0m d out 0m+1 t rp (bank 0) (1) c a s latency = 2, burstlength = full page don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 43 rev. a 07/21/04 read cycle / ping-pong operation (bank switching) clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 0 bank 0 bank 0 bank 0 bank 1 bank 1 bank 1 bank 0 or 1 bank 0 or 1 no pre no pre t ch t ah t as t qmd t cs t ac t ac t ac t ac t rcd (bank 0) t ras (bank 0) < act 0 > < act 0 >< act1 > < read 0 > < reada 0 >< reada 1 > < read 1 >< pre 0 >< pre 1 > t ah t as t cks t cka row row row row row column column auto pre auto pre row t lz t lz t rcd (bank 1) t ras (bank 1) t rc (bank 1) t cac (bank 1) t cac (bank 1) t rc (bank 0) t rp (bank 0) t rp (bank1) t rcd (bank 0) t ras (bank 0) t rc (bank 0) t rrd (bank 0 to 1) t oh t oh t oh t oh t hz t hz d out 0m d out 0m+1 d out 1m d out 1m+1 (1) (1) c a s latency = 2, burstlength = 2 don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 44 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write cycle clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t7 t6 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 bank 0 or 1 bank 0 and 1 no pre t ch t ah t as t cs t ds t ds t ds t ds t dh t ras t rc < pre > < pall > < act > < act >< writ > t ah t as t cks t cka row row row column m row t rcd t dh t dh t dh t rp t dpl t rcd t ras t rc d in m d in m+2 d in m+1 d in m+3 bank 1 bank 0 bank 1 bank 0 bank 1 bank 0 (1) c a s latency = 2, burstlength = 4 don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 45 rev. a 07/21/04 write cycle / auto-precharge clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t7 t6 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 auto pre t ch t ah t as t cs t ds t ds t ds t ds t dh t ras t rc < act > < act >< writa > t ah t as t cks t cka row row row column m row t rcd t dh t dh t dh t rp t dal t rcd t ras t rc d in m d in m+2 d in m+1 d in m+3 bank 1 bank 0 bank 1 bank 0 (1) c a s latency = 2, burstlength = 4 don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 46 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write cycle / full page clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t259 t258 t260 t261 t262 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 0 or 1 bank 0 row column m row t ras t rc < act 0 >< writ0 > < bst >< pre 0 > t rcd t ch t dpl t rp t ds t ds t ds t ds t dh t dh t dh t dh d in 0m d in 0m+2 d in 0m+1 d in 0m-1 d in 0m (1) cas latency = 2, burst length = full page don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 47 rev. a 07/21/04 write cycle / ping-pong operation clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 0 bank 0 bank 0 bank 0 bank 1 bank 1 bank 0 or 1 no pre no pre t ch t ah t as t cs t ds t ds t rcd (bank 0) t ras (bank 0) < act 0 >< act 1 > < writ 0 > < writa 0 >< writa 1 > < writ 1 >< pre 0 >< act 0 > t ah t as t cks t cka row row row row row column column auto pre auto pre row t rcd (bank 1) t ras (bank 1) t rc (bank 1) t rc (bank 0) t rcd (bank 0) t rp (bank 0) t ras (bank 0) t rc (bank 0) t rrd (bank 0 to 1) t dpl t dpl t dh t dh t ds t dh t dh d in 0m t ds t ds t dh t ds t dh t dh t dh t ds t ds d in 0m+1 d in 0m+2 d in 0m+3 d in 1m d in 1m+1 d in 1m+2 d in 1m+3 (1) (1) don't care undefined cas latency = 2, burst length = 2 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 48 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle / page mode clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 bank 0 bank 0 bank 0 bank 1 bank 0 or 1 bank 0 and 1 bank 1 t ch t ah t as t lz t cs t ras t rc < act >< read > < reada > < read > < read > < pall > < pre > t ah t as t cks t cka row column m column n column o no pre no pre no pre auto pre row t rcd t cac t cac t cac t rql t hz t rp t qmd bank 1 bank 0 bank 1 t ac t ac t oh t ac t ac t ac t ac t oh t oh t oh t oh t oh d out md out m+1 d out nd out n+1 d out od out o+1 (1) (1) (1) don't care undefined cas latency = 2, burst length = 2 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 49 rev. a 07/21/04 read cycle / page mode; data masking clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 bank 0 bank 0 bank 0 bank 1 bank 0 or 1 bank 0 and 1 no pre bank 1 t qmd t ah t as t lz t cs t ras t rc < act >< read > < reada, enb > < read, enb > < mask > < pall > < pre > t ah t as t cks t cka row column m column n column o no pre no pre no pre auto pre row t ch t rcd t cac t cac t cac t rql t hz t hz t rp t qmd bank 1 bank 0 bank 1 t ac t lz t ac t oh t ac t ac t ac t oh t oh t oh t oh d out md out m+1 d out nd out od out o+1 (1) (1) (1) don't care undefined cas latency = 2, burst length = 2 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 50 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write cycle / page mode clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 bank 0 bank 0 bank 0 bank 1 bank 0 or 1 bank 0 and 1 bank 1 t ch t ah t as t cs t ras t rc < act >< writ > < writa > < writ > < writ > < pall > < pre > t ah t as t cks t cka row column m column n column o no pre no pre no pre auto pre row t rcd t dpl t rp bank 1 bank 0 bank 1 t ds t ds t ds t ds t dh t ds t dh t dh t dh t ds t dh t dh d in m d in n d in m+1 d in n+1 d in o d in o+1 (1) (1) (1) don't care undefined cas latency = 2, burst length = 2 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 51 rev. a 07/21/04 write cycle / page mode; data masking clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 bank 0 bank 0 bank 0 bank 1 bank 1or 0 bank 0 and 1 bank 1 t ch t ah t as t cs t ras t rc < act >< writ >< writ > < writa > < writ > < mask > < pall > < pre > t ah t as t cks t cka row column m column n column o no pre no pre no pre auto pre row t rcd t dpl t rp bank 1 bank 0 bank 1 t ds t ds t ds t dh t ds t dh t dh t dh t ds t dh d in m d in n d in m+1 d in o d in o+1 (1) (1) (1) don't care undefined cas latency = 2, burst length = 2 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 52 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle / clock suspend clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre auto pre t ah t as t cs t ckh t ah t as t cks t cka t cks bank 1 bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 bank 0 bank 0 and 1 bank 0 or 1 row row row column m row t qmd t lz t ras t rc t rc < act 0 > < act > < read > < read a > < spnd >< spnd >< pre > < pall > t rcd t cac t ac t ac t oh t oh t ch d out md out m+1 t hz t rp t ras (1) don't care undefined cas latency = 2, burst length = 2 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 53 rev. a 07/21/04 write cycle / clock suspend clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre auto pre t ah t as t cs t ckh t ah t as t cks t cka t cks bank 1 bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 bank 0 bank 0 and 1 bank 0 or 1 row row row column m row t ds t ras t rc t rc < act > < act > < writ, spnd > < writa, spnd > < spnd >< pre > < pall > t rcd t ch t dh t dh t ds t dpl t rp t ras d in md in m+1 (1) don't care undefined cas latency = 2, burst length = 2 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 54 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle / precharge termination clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre auto pre no pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 1 bank 0 bank 0 bank 0 bank 0 or 1 row row row column m column n row t qmd t lz t ras t rc t rc < act 0 > < act > < read 0 > < pre 0 >< read > < reada > t rcd t cac t rql t rp t rcd t ac t ac t oh t ac t hz t oh t oh t ch d out md out m+2 t ras t cac bank 1 d out m+1 (1) (1) don't care undefined cas latency = 2, burst length = 4 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 55 rev. a 07/21/04 write cycle / precharge termination clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre auto pre no pre t ah t as t ah t as t cks t cka bank 0 bank 0 bank 1 bank 0 bank 0 bank 0 bank 0 or 1 row row row column m column n row t ras t rc t rc < act 0 > < act > < writ 0 > < pre 0 >< writ > < writa > t rcd t rp t rcd t ras bank 1 d in 0m d in 0n d in 0m+1 d in 0m+2 t ds t ds t ds t ds t dh t dh t dh t dh t cs t ch t cs t cs t ch (1) (1) don't care undefined cas latency = 2, burst length = 4 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 56 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle / byte operation clk cke cs ras cas we a0-a9 a10 a11 ldqm udqm dq8-15 dq0-7 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 1 bank 0 and 1 bank 0 or 1 no pre auto pre t ch t ah t as t cs t cs t ch t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 bank 0 row column m row t qmd t qmd t ras t rc < act > < act > < read > < reada > < masku > < maskl > < enbu, maskl > < pall > < pre > t rcd t cac t qmd t rql t rcd t ras t rc t rp t ac t hz t oh t ac t ac t lz t lz t lz d out m d out m d out m+2 d out m+1 d out m+3 t oh t oh t oh t ac t ac t oh row row (1) don't care undefined cas latency = 2, burst length = 4 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 57 rev. a 07/21/04 write cycle / byte operation clk cke cs ras cas we a0-a9 a10 a11 ldqm udqm dq8-15 dq0-7 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 1 bank 0 and 1 bank 0 or 1 no pre auto pre t ch t ah t as t cs t cs t ch t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 bank 0 row column m row t ras t rc < act > < act > < writ > < writa > < mask > < maskl > < enb > < pall > < pre > t rcd t dpl t rcd t ras t rc t rp row row t dh t ds t ds t dh t ds t dh t ds d in m d in m d in m+3 t dh t dh t ds d in m+1 d in m+3 (1) don't care undefined cas latency = 2, burst length = 4 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 58 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle, write cycle / burst read, single write column n clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 and 1 bank 0 or 1 no pre no pre auto pre t ch t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 bank 1 bank 0 row column m row t qmd t hz t lz t ras t rc < act >< read > < writa > < writ > < pall > < pre > t rcd t cac t dpl t rp t ac t ac t oh t ac t ac t oh t dh t ds t oh d out md out m+1 d out m+2 t oh d out m+3 d in n (1) (1) don't care undefined cas latency = 2, burst length = 4 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 59 rev. a 07/21/04 read cycle clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 and 1 bank 0 or 1 no pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 bank 1 bank 0 row row row column m row t qmd t lz t ras t rc < act >< read > < act > < pre > < pall > t rcd t cac t rql t rp t rcd t ac t ac t oh t ac t ac t oh t ch t oh d out md out m+1 d out m+2 t oh t hz d out m+3 t rc t ras (1) don't care undefined cas latency = 3, burst length = 4 note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 60 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle / auto-precharge clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 auto pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 row row row column row t qmd t lz t ras t rc < act >< reada > < act > t rcd t cac t pql t rp t rcd t ac t ac t oh t ac t ac t oh t ch t oh d out md out m+1 d out m+2 t oh t hz d out m+3 t rc t ras (1) cas latency = 3, burst length = 4 don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 61 rev. a 07/21/04 read cycle / full page clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t262 t263 t264 t265 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 0 or 1 bank 0 row column row t lz t ras (bank 0) t rc (bank 0) < act 0 >< read0 > < bst >< pre 0 > t rcd (bank 0) t cac (bank 0) t rbd t ac t ac t oh t ac t ac t ac t oh t ch t oh d out 0m d out 0m+1 d out 0m-1 t oh t hz t oh d out 0m d out 0m+1 t rp (bank 0) (1) cas latency = 3, burst length = full page don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 62 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle / ping pong operation (bank switching) clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 0 bank 1 bank 0 bank1 bank 0 bank 1 bank 0 bank 0 or 1 bank 0 or 1 no pre no pre t ch t ah t as t qmd t cs t ac t ac t ac t ac t rcd (bank 0) t ras (bank 0) < act 0 > < act 0 > < act1 >< read 0 > < reada 0 >< reada 1 > < read 1 >< pre 0 >< pre 1 > t ah t as t cks t cka row row row row row column column auto pre auto pre row t lz t ras (bank 1) t rc (bank 1) t rcd (bank 1) t cac (bank 1) t cac (bank 0) t rc (bank 0) t rql (bank 0) t rp (bank 0) t rcd (bank 0) t ras (bank 0) t rp (bank1) t rc (bank 0) t rrd (bank 0 to 1) t oh t oh t oh t oh t hz d out 0m d out 0m+1 d out 1m d out 1m+1 (1) (1) cas latency = 3, burst length = 2 don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 63 rev. a 07/21/04 write cycle clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t7 t6 t8 t9 t10 t11 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 bank 0 or 1 bank 0 and 1 no pre t ch t ah t as t cs t ds t ds t ds t ds t dh t ras t rc < pre > < pall > < act > < act >< writ > t ah t as t cks t cka row row row column row t rcd t dh t dh t dh t rp t dpl t rcd t ras t rc d in m d in m+2 d in m+1 d in m+3 bank 1 bank 0 bank 1 bank 0 bank 1 bank 0 t12 (1) cas latency = 3, burst length = 4 don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 64 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write cycle / auto-precharge clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t7 t6 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 auto pre t ch t ah t as t cs t ds t ds t ds t ds t dh t ras t rc < act > < act >< writa > t ah t as t cks t cka row row row column row t rcd t dh t dh t dh t rp t dal t rcd t ras t rc d in m d in m+2 d in m+1 d in m+3 bank 1 bank 0 bank 1 bank 0 t11 t12 (1) cas latency = 3, burst length = 4 don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 65 rev. a 07/21/04 write cycle / full page clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t259 t6 t260 t261 t262 t263 t264 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 0 or 1 bank 0 row column row t ras t rc < act 0 >< writ0 > < bst >< pre 0 > t rcd t ch t dpl t rp t ds t ds t ds t ds t dh t dh t dh t dh d in 0m d in 0m+2 d in 0m+1 d in 0m-1 d in 0m (1) cas latency = 3, burst length = full page don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 66 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write cycle / ping-pong operation (bank switching) clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 0 bank 0 bank 0 bank 1 bank 1 bank 0 or 1 no pre no pre t ch t ah t as t cs t ds t ds t rcd (bank 0) t ras (bank 0) < act 0 >< act 1 > < writ 0 > < writa 0 >< writa 1 > < writ 1 >< pre 0 >< act 0 > t ah t as t cks t cka row row row row row column column auto pre auto pre row t rcd (bank 1) t ras (bank 1) t rc (bank 1) t rc (bank 0) t rcd t rp (bank 0) t ras t rc t rrd (bank 0 to 1) t dpl (bank 0) t dpl t dh t dh t ds t dh t dh d in 0m t ds t ds t dh t ds t dh t dh t dh t ds t ds d in 0m+1 d in 0m+2 d in 0m+3 d in 1m d in 1m+1 d in 1m+2 d in 1m+3 t11 t12 bank 0 bank 1 (1) (1) cas latency = 3, burst length = 4 don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 67 rev. a 07/21/04 read cycle / page mode clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 bank 0 bank 0 bank 0 bank 1 bank 0 or 1 bank 0 and 1 bank 1 t ch t ah t as t lz t cs t ras t rc < act >< read > < reada > < read > < read > < pall > < pre > t ah t as t cks t cka row column m column n column o no pre no pre no pre auto pre row t rcd t cac t cac t cac t rql t hz t rp t qmd bank 1 bank 0 bank 1 t ac t ac t oh t ac t ac t ac t ac t oh t oh t oh t oh t oh d out md out m+1 d out nd out n+1 d out od out o+1 t11 t12 (1) (1) (1) cas latency = 3, burst length = 2 don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 68 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 read cycle / page mode; data masking cas latency = 3, burst length = 2 clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 bank 0 bank 0 bank 0 bank 1 bank 0 or 1 bank 0 and 1 bank 1 t qmd t ah t as t lz t cs t ras t rc < act >< read >< read >< enb > < reada, mask > < read, mask > < pall > < pre > t ah t as t cks t cka row column m column n column o no pre no pre no pre auto pre row t ch t rcd t cac t cac t cac t rql t hz t rp t qmd bank 1 bank 0 bank 1 t ac t ac t oh t ac t ac t ac t oh t oh t oh t oh d out md out m+1 d out nd out od out o+1 t11 t12 (1) (1) (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 69 rev. a 07/21/04 write cycle / page mode cas latency = 3, burst length = 2 clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 0 bank 0 bank 0 bank 0 bank 1 bank 0 or 1 bank 0 and 1 bank 1 t ch t ah t as t cs t ras t rc < act >< writ > < writa > < writ > < writ >< mask > < pall > < pre > t ah t as t cks t cka row column m column n column o no pre no pre no pre auto pre row t rcd t dpl t rp bank 1 bank 0 bank 1 t ds t ds t ds t dh t ds t dh t dh t dh t ds t dh d in m d in n d in m+1 d in o d in o+1 t11 t12 (1) (1) (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 70 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write cycle / page mode; data masking cas latency = 3, burst length = 2 clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 bank 0 bank 0 bank 0 bank 1 bank 1or 0 bank 0 and 1 bank 1 t ch t ah t as t cs t ras t rc < act >< writ >< writ > < writa > < writ > < mask > < pall > < pre > t ah t as t cks t cka row column m column n column o no pre no pre no pre auto pre row t rcd t dpl t rp bank 1 bank 0 bank 1 t ds t ds t ds t dh t ds t dh t dh t dh t ds t dh d in m d in n d in m+1 d in o d in o+1 (1) (1) (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 71 rev. a 07/21/04 read cycle / clock suspend cas latency = 3, burst length = 2 clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre auto pre t ah t as t cs t ckh t ah t as t cks t cka t cks bank 1 bank 0 bank 0 bank 1 bank 0 bank 0 and 1 bank 0 or 1 row column m row t qmd t lz t ras t rc < act >< read > < read a > < spnd >< spnd >< pre > < pall > t rcd t cac t ac t ac t oh t oh t ch d out md out m+1 t hz t rp t12 bank 1 (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 72 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write cycle / clock suspend cas latency = 3, burst length = 2 clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre auto pre t ah t as t cs t ckh t ah t as t cks t cka t cks bank 1 bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 bank 0 bank 0 and 1 bank 0 or 1 row row row column m row t ds t ras t rc t rc < act > < act > < writ, spnd > < writa, spnd > < spnd >< pre > < pall > t rcd t ch t dh t dh t ds t dpl t rp t ras d in md in m+1 t11 t12 (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 73 rev. a 07/21/04 read cycle / precharge termination cas latency = 3, burst length = 2 clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 0 row row row column m row t qmd t lz t ras t rc t rp < act 0 > < act > < read 0 > < pre 0 > t rcd t cac t rql t rp t rcd t ac t ac t oh t ac t hz t oh t oh t ch d out md out m+2 t ras bank 1 d out m+1 t11 t12 bank 0 bank 0 or 1 (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 74 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write cycle / precharge termination cas latency = 3, burst length = 4 clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as no pre t ah t as t ah t as t cks t cka bank 0 bank 0 bank 0 row row row column m row t rc t rp < act 0 > < act > < writ 0 > < pre 0 > t rcd t rp t rcd t ras bank 1 d in 0m d in 0m+1 d in 0m+2 t ds t ds t ds t dh t dh t dh t11 t12 t ch t ch t cs t cs bank 0 bank 0 or 1 t ras (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 75 rev. a 07/21/04 read cycle / byte operation cas latency = 3, burst length = 4 clk cke cs ras cas we a0-a9 a10 a11 ldqm udqm dq8-15 dq0-7 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 1 bank 0 and 1 bank 0 or 1 no pre auto pre t ch t ah t as t cs t cs t ch t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 bank 0 row column m row t qmd t qmd t ras t rc < act > < act > < read > < reada > < masku > < maskl > < enbu, maskl > < pall > < pre > t rcd t cac t qmd t rql t rcd t ras t rp t rp t ac t hz t oh t hz t hz t ac t ac t lz t lz t lz d out m d out m d out m+2 d out m+1 d out m+3 t oh t oh t ac t ac t oh row row t12 (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 76 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 write cycle / byte operation cas latency = 3, burst length = 4 clk cke cs ras cas we a0-a9 a10 a11 ldqm udqm dq8-15 dq0-7 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 1 bank 0 and 1 bank 0 or 1 no pre auto pre t ch t ah t as t cs t cs t ch t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 bank 0 row column m row t ras t rc < act > < act > < writ > < writa > < mask > < maskl > < enb > < pall > < pre > t rcd t dpl t rcd t ras t rp t rp row row t dh t ds t ds t dh t ds t dh t ds d in m d in m d in m+3 t dh t dh t ds d in m+1 d in m+3 t12 t11 (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 77 rev. a 07/21/04 read cycle, write cycle / burst read, single write cas latency = 3, burst length = 2 column n clk cke cs ras cas we a0-a9 a10 a11 dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t ck t chi t cl t ch t cs t ch t cs t ch t cs t ch t cs t ah t as bank 1 bank 0 and 1 bank 0 or 1 no pre no pre auto pre t ch t ah t as t cs t ah t as t cks t cka bank 0 bank 0 bank 1 bank 1 bank 0 bank 1 bank 0 row column m row t qmd t hz t lz t ras t rc < act >< read > < writa > < writ > < pall > < pre > t rc t cac t dpl t rp t ac t ac t dh t ds t oh d out m t oh d out m+1 d in n t11 t12 (1) (1) don't care undefined note 1: a8,a9 = don?t care .
is42s16100c1 issi ? 78 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 07/21/04 ordering information commercial range: 0 c to 70 c frequency speed (ns) order part no. package 200 mhz 5 is42s16100c1-5t 400-m il tsop ii 200 mhz 5 is42s16100c1-5tl 400-mil tsop ii, lead-free 166 mhz 6 IS42S16100C1-6T 400-m il tsop ii 166 mhz 6 IS42S16100C1-6Tl 400-mil tsop ii, lead-free 143mhz 7 is42s16100c1-7t 400-mil tsop ii 143mhz 7 is42s16100c1-7tl 400-mil tsop ii, lead-free industrial range: -40 c to 85 c frequency speed (ns) order part no. package 143mhz 7 is42s16100c1-7ti 400-mil tsop ii 143mhz 7 is42s16100c 1-7tli 400-mil tsop ii, lead-free
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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